Digital signal processing

Why two levels resist noise

An analogue signal carries its information in its exact shape, and that is its weakness. Every metre of cable adds a little random noise, and once noise is mixed in no circuit can tell it from signal. Amplifying a tired analogue signal amplifies the noise with it, so each leg of a long link leaves the signal permanently worse.

A digital signal gives up the shape entirely. Only two levels mean anything, logic 0 near 0 V and logic 1 near the supply voltage, and the receiver makes one crude test, above the threshold or below it? Noise that would wreck an analogue waveform leaves a 1 still recognisably a 1. There is a genuine margin for error, and small noise sits inside it.

Better still, a digital signal can be regenerated. A repeater partway along the route reads each incoming pulse as 0 or 1, then issues a brand-new, full-height pulse at the nominal levels. It does not amplify the old signal, it replaces it, and the noise collected so far is discarded. While every sample still falls on the correct side of the threshold the message crosses a continent unchanged; let noise or timing error reach the decision margin first and bits get misread, which is why repeaters are spaced to stay well inside it. Transmitted power is beside the point, and digital links usually use less of it.

The six gates

The circuits that act on logic levels are gates. A gate's output depends only on its present inputs, so the whole behaviour fits in a truth table, one row per input combination. The simplest is NOT, one input, one output, always the opposite: input 0 gives 1, input 1 gives 0. The remaining five take two inputs, so their tables have four rows:

Three of these are worth learning as sentences. AND outputs 1 only when both inputs are 1. OR outputs 1 when at least one input is 1. EOR, exclusive-OR, outputs 1 when the inputs differ, and that last row is the one that separates it from OR. NAND and NOR are simply AND and OR with the answer inverted, drawn with a small circle on the output, and each of them alone can be wired up to build every other gate.

Combinational design is reading Boolean sentences in both directions. A specification in words becomes an expression, the expression becomes gates. The habit worth building is to write the full truth table, every input combination in binary counting order, because it brings out the cases you did not think about.

The half-adder

Binary arithmetic in one column is small enough to build by inspection. Adding bits A and B gives 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, and 1 + 1 = 10, which is the number two, written as sum 0 carry 1. Now stare at the two output columns. The sum is 1 exactly when the inputs differ, and the carry is 1 exactly when both inputs are 1. Those are tables you already know.

So a half-adder is one EOR gate for the sum and one AND gate for the carry, wired to the same pair of inputs. It is the standard exam example of combinational design, a truth table recognised as a pair of known gates. Chain half-adders with provision for an incoming carry and you have the adder at the heart of every processor.

Memory, and counting by halving

Gates have no memory; release a switch and the output reverts immediately. Sequential circuits add the missing ingredient with the D-type flip-flop, a one-bit memory. It has a data input D, a clock input, and an output Q. On each rising clock edge it copies whatever is on D to Q, then holds Q frozen until the next edge, ignoring D completely in between. Registers and other small fast storage are rows of these, one per bit; bulk memory uses denser cells instead, a capacitor per bit in DRAM and charge-trapping transistors in flash.

One wiring trick turns storage into rhythm. Connect the flip-flop's inverted output back to its own D input and every clock edge loads the opposite of what Q held, so Q toggles at each edge. Two clock cycles pass before Q completes one full cycle of its own, so Q runs at half the clock frequency, a clean square wave. Feed that stage's inverted output onward as the clock of a second stage and the halving repeats. For n stages,

Read all the Q outputs at once, last stage first, and the same chain is a binary counter. The outputs step through 00, 01, 10, 11 and onward, one count per clock pulse, rolling over after 2ⁿ$2^{n}$2^n states. Counting and frequency division are the same circuit described two ways.

Counters that stop where you want them to

A plain chain always runs to 2ⁿ$2^{n}$2^n and rolls over, and that is rarely the number anybody wants. Wire the outputs that are high at the unwanted count into a NAND gate, and take its output to the reset input of every stage. The instant that count appears the gate clears the whole chain, so the count never persists there and the chain starts again from zero instead. Detect ten, 1010, and the chain counts 0000 up to 1001 and resets: a modulo-10, or decade, counter. Any modulus is available by choosing which outputs feed the gate.

The decade is the useful one, because a decimal digit has exactly ten states. Four bits holding 0000 to 1001 and nothing above is binary-coded decimal, and a BCD counter is a decade counter read as one decimal digit. Cascade them, the last output of each decade clocking the next, and the units decade rolls over once per ten pulses while the tens decade rolls over once per hundred, so four of them drive a display reading 0 to 9999 with no arithmetic in between. A frequency meter is that row of BCD counters behind a gate that lets pulses through for exactly one second.

Counting backwards needs one extra connection per stage. Each flip-flop copies D on a rising edge, so a stage clocked from the previous stage's inverted output steps the count up, and the same stage clocked from Q instead steps it down. An up/down counter brings both routes to a pair of gates in every stage and lets a single direction input choose between them, which is what a lift controller requires when it has to track how many floors are left in either direction.

A Johnson counter gives up the ripple altogether. Put n flip-flops in a row, all clocked together, each output feeding the next one's D input so that a pattern shifts one place along the row per pulse, and then bring the last stage's inverted output back to the first stage's D. From 0000 the row fills with ones from the left, 1000, 1100, 1110, 1111, and the inverted feedback then fills it with zeros the same way, 0111, 0011, 0001, 0000. Four stages therefore cycle through eight states rather than sixteen, and n stages through 2n.

Two of those states are worth the waste. Only one output changes at each step, so the outputs never pass through a wrong combination on their way to the right one as a ripple chain does, and any single state can be recognised by a two-input gate rather than an n-input one. Where a ripple counter is asked only for a number, a Johnson counter is asked for clean, glitch-free timing signals in a fixed order.

The astable, which supplies the clock

Every counter above waits on a clock, and something has to make one. A comparator will, once it is given a memory of its own. Feed a fraction of the output back to the non-inverting input, which is positive feedback, and the circuit holds whichever rail it has reached until the other input is dragged past the threshold that fraction sets. Now charge a capacitor towards the output through a resistor and take the inverting input from it. The capacitor climbs, crosses the upper threshold, and the output flips; it then falls towards the other rail, crosses the lower threshold, and the output flips back. Neither state is stable, so it never stops. That is an astable.

All the timing lives in the charging. Each interval lasts a fixed multiple of the RC of whichever path is charging the capacitor during it, the multiple set by where the thresholds sit, so doubling that resistance doubles that interval and touches nothing else. Give the two directions separate paths, a pair of resistors each with a diode that lets current through one way only, and the high time and the low time become independent of each other.

Three numbers describe the output, and questions ask for them by name. The pulse width is the length of the high part on its own, t₁$t_{1}$t_1. The period is t₁ + t₂$t_{1} + t_{2}$t_1 + t_2 and the frequency is its reciprocal. The mark-to-space ratio is the high time divided by the low time, t₁/t₂$t_{1}/t_{2}$t_1/t_2, quoted as a ratio. The duty cycle is the high time as a fraction of the whole period, t₁/(t₁ + t₂)$t_{1}/(t_{1} + t_{2})$t_1/(t_1 + t_2), quoted as a percentage. Equal intervals give a square wave, mark-to-space 1:1 at a duty cycle of 50%.

A counter responds to any of those settings, since it acts on an edge, provided the pulse stays wide enough and its edges sharp enough to meet the counter's own timing requirements; make a pulse too narrow or too slow-edged and even an edge-triggered input misses it.

For a load switched by a MOSFET the duty cycle is what matters. The duty cycle is the fraction of the time the channel is open, so it fixes the average power the load receives: modelling the lamp as a constant resistance, one fed at 20% duty from a 12 V supply is being given a fifth of the power it would take at 100% (a real filament's resistance shifts with temperature, so the proportion belongs to the model), while the switch itself stays cool because it is either fully on or fully off.